A) Field of the Invention
This invention relates to a solid state imaging device, especially to a structure of a solid state imaging device for a digital still camera.
B) Description of the Related Art
Recently the number of pixels in a digital still camera (hereinafter called DSC) follows a course of increase, and there is a DSC having over ten million pixels. It is obvious that an increase in the number of pixels leads to improvement of resolution; however, it also leads to various problems. For example, a quantity of output data will increase, a reading time for one frame (screen) becomes longer and a frame rate will be lowered. in order to prevent the lowering of the frame rate, it is necessary for the DSC to be driven faster (to have a high frame rate). Moreover, for example, increase in the number of pixels means that increase in a quantity of data to be stored; therefore, it causes increase in a size of a storage medium. Furthermore, a pixel size becomes smaller to increase the number of pixels without enlarging a size of a chip in the solid-state imaging device, and It lowers sensitivity of the solid-state imaging device, which is the most important feature of the solid state imaging device. Further, it will be difficult to generate a high quality motion picture (e.g., VGA quality) at a proper frame rate (e.g., 30 fps).
Generally an image taken by the DSC will be printed onto L-size (89×127 mm) photo paper, 4×6″ photo paper or a post card. The number of pixels sufficient for realizing necessary resolution to print the image onto such papers is two to three millions. Therefore, it is wasteful to take a picture for the papers in those sizes by using a solid-state imaging device having ten million pixels in its maximum performance, and it further causes decrease in resolution and in quality of a motion picture.
FIG. 9 is a schematic plan view of a conventional solid state imaging device 800.
The solid state imaging device 800 is the most commonly used interlace-type CCD (ITCCD) as a conventional solid state imaging device, A large number of photoelectric conversion elements (pixels) 812 are arranged in a tetragonal matrix in a light receiving region 802. A vertical electric charge transfer device (vertical charge coupled device: VCCD) 814 that reads out signal charges generated at the photoelectric conversion elements 812 and vertically transfers is formed including transfer electrodes and a vertical transfer channel for each column of the photoelectric conversion elements 812 and transfers the signal charges generated at photoelectric conversion elements 812 in a vertical direction.
In the drawing, a horizontal electric charge transfer device (horizontal charge coupled device: HCCD) 803 that transfers electric charges transferred by the VCCD 814 to a peripheral circuit 804 line by line is formed under the light receiving region 802. Also, pixel lines on lines indicated with white arrows are first field lines in an interlace scanning method, and pixel lines on lines indicated with black arrows are second field lines.
A color filter arrangement corresponding to each pixel is presented with letters “R, G and B” in each pixel. Here in this specification, R, G and B respectively indicate red, green and blue. The color filter arrangement adopted in this solid state imaging device 800 is so-called Bayer arrangement and generally used for the solid state imaging device as an imaging device for a digital still camera (DSC).
In, the DSC, image information is extracted in the form of an electric signal; therefore, it is comparatively easy to generate a motion picture by reading out field images continuously. It is common to display the motion picture on a liquid crystal display monitor, which corresponds to a finder of a conventional camera, by using the above-described feature.
At least 15 fps is necessary to smoothly express a motion of a target. Further to enjoy displaying the motion picture on a TV screen, 30 fps is necessary. However, as described in the above, it will be hard to read signals at a high frame rate when the number of pixels is increased for high resolution. Although a line curtailed operation in which a signal line is not read out at a predetermined interval to solve the problem, it may not be an efficient way because the line curtailed operation wastes the expressly taken signal electric charges. Therefore, it is efficient if the effective number of pixels can be reduced by adding the signals without curtailing the signal lines. That is, an adding operation reduces the number of signal pixels to increase quantity of signal for one pixel so that higher resolution can be realized.
FIG. 10A to FIG. 10D are diagrams showing signal arrangements read by the conventional ITCCD solid state imaging device 800.
FIG. 10A is a diagram shoving a signal arrangement of the first field, and FIG. l0B is a diagram showing a signal arrangement of the second field. Both of the first field and the second field add same colored signals in every two lines. As a result, as shown in FIG. 10C, a signal arrangement of a vertical two-pixel addition field synthesized frame generated by synthesizing each field after the vertical addition can be obtained. Moreover, the conventional reading method for the ITCCD cannot reproduce a colored motion picture. Because each field includes only two types of signals such as G and R color signals or G and B color signals, one field cannot generate color signals including all of R, G, and B color signals. Since the color signal including R, G and B can be naturally generated after the field synthesis, the color signal after the synthesis, for example, can be used for a still picture with decreased number of pixels. In this case, sensitivity will be about twice by the addition of the signals.
FIG. 10D is a diagram showing spatial sampling centers after the vertical additions. The sampling points of G formed by the vertical addition of the first field with the Bayer Arrangement will be on lines indicated by white arrows, and the sampling points of G formed by the vertical addition of the second field with the Bayer Arrangement will be on lines indicated by black arrows. As obvious from the drawing, the sampling centers of the G signals after the vertical additions do not have regular intervals. Also, since the spatial sampling centers overlap with each another in wide areas, resolution obtained for the number of the sampling points will be lowered.
FIG. 11 is a schematic plan view of a conventional solid state imaging device 200.
The solid state imaging device 200 is composed including a light receiving region 202 including a large number of photoelectric conversion elements 212 and vertical electric charge transfer devices (VCCD) 214 that vertically transfer signal charges generated at the photoelectric conversion elements 212, a horizontal electric charge transfer device (HCCD) 203 that horizontally transfers the signal charges transferred by the VCCDs 214 and an output amplifier 204.
The light-receiving region 202 in the imaging device adopting the pixel interleaved array CCD (PIACCD) as shown in the drawing consists of the plurality of photoelectric conversion elements configured in a pixel interleaved arrangement. Between each row of the photoelectric conversion elements, a vertical electric charge transfer device 214 which reads the signal electric charges generated by the photoelectric conversion elements 212 and transfers them to a vertical direction are arranged by traversing in the spaces among the photoelectric conversion elements 212 in the vertical direction. Transfer channels are positioned in the zigzag spaces formed by the pixel interleaved arrangement, and the adjacent transfer channels apart from each ether via the photoelectric conversion elements and come closer to each other via the channel stop region (not shown in the drawing). For example, the details of the pixel interleaved arrangement can be found in Japanese Laid-Open Patent Hei 10-136391 and Tetsuo Yamada, et al, February, 2000, “A Progressive Scan CCD Irnager for DSC Applications”, ISSCC Digest of Technical Papers, Page 110 to 111.
The vertical electric charge transfer device 214 is consisted of the vertical transfer channel (not shown in the drawing) and transfer electrodes which are formed over the vertical transfer channel via an insulating film (not shown in the drawing) and traversing between the photoelectric conversion elements 212 to the horizontal direction.
In the drawing, the color of the color filter (for example, green, blue or red) corresponding to each pixel is indicated by the letter G, B and R in each of the pixels 212. Also, pixel lines on lines indicated with white arrows are first field lines in the interlace scanning method, and pixel lines on lines indicated with blacks arrow are second field lines.
In the PIACCD shown in the drawing, the improved addition disclosed in Japanese Patent Application No. 2004-38266, filed by the same inventor as the present invention can be carried out. When the signals for the first field lines are read, the first G-line and the second G-line, and the fifth G-line and the sixth G-line are read. When the signals for the second field lines are read, the third G-line and the fourth G-line, the seventh G-line and the eighth G-line are read. As shown in the drawing, each G-line is formed along a solid line repeatedly connecting a center of each pixel in a zigzag form.
FIG. 12A to FIG. 12D are diagrams showing signal arrangements read by the conventional PIACCD solid state imaging device 200.
FIG. 12A is a diagram showing a signal arrangement of the first field, and FIG. 12B is a diagram showing a signal arrangement of the second field. G-lines adjoining each other to vertical direction exist in each field. These adjoining G-lines are added vertically. That is, the first G-lines and the second G-lines, the fifth G-lines and the sixth G-lines are respectively added in the first field, and the third G-lines and the fourth G-lines, and the seventh G-lines and the eighth G-lines are respectively added in the second field. As a result, as shown in FIG. 12C, a signal arrangement of a vertical two-pixel addition field synthesized frame generated by synthesizing each field after the vertical additions can be obtained.
FIG. 12D is a diagram showing spatial sampling centers after the vertical additions. In this embodiment, because the G-lines (the signals of the G-pixels) that are originally vertically adjoining are added, centers of the sampling points of G in a vertical direction after the field synthesis will be on a line indicated by white arrows after the vertical addition for the first field and on lines indicated by black arrows after the vertical addition for the second field. Therefore, as shown in FIG. 12D, the centers of the sampling points are arranged with regular vertical intervals.
In this improved addition, the vertical resolution is reduced half. Further, regarding to the horizontal addition, the resolution of G will be less than half. The resolutions of R and B will be also less than half.